The invention relates generally to the field of serial communication between components of a system, and more particularly to a protocol for an addressable serial peripheral interface.
Serial interfaces are widely used for data communications between components of a system, and in particular between a control unit and its peripherals. One common example of such a serial interface is the serial peripheral interface (SPI) described in U.S. Pat. No. 4,958,277 issued Sep. 18, 1990 to Hill et al, entitled “Queued Serial Peripheral Interface for Use in a Data Processing System”, and in U.S. Pat. No. 7,069,352 issued Jun. 27, 2006 to Pezzini entitled “Serial Peripheral Interface and Related Methods”, the entire contents of both of which are incorporated herein by reference.
The SPI is a full duplex synchronous data link in which devices communicate in a master slave arrangement. One device acts as the SPI master which initiates a data frame by outputting a serial clock, conventionally denoted SCLK. SCLK is used by the slave to output serial data for transmission to the master, and/or to clock in serial data received from the master. Each SPI device exhibits a serial data output line and a serial data input line, labeled respectively as master out/slave in (MOSI) and master in/slave out (MISO). A plurality of slave devices may be used provided that the master supplies a separate slave select output, denoted SS, for each slave device. Unfortunately, such a system requires a dedicated SS pin for each slave device, which is costly. In an embodiment in which a plurality of slaves are provided, the SPI is known as an SPI bus, since all communication lines are shared.
An additional difficulty with an SPI bus is the lack of built in acknowledgement. In particular, the master in an SPI bus may transmit data to a non-existent slave, without receiving an error indication. Furthermore data transmitted to the slave, or read from the slave by the master, may incur errors in transmission. Typically, an error detection mechanism such as a cyclic redundancy check (CRC) is utilized, however no mechanism is supplied to confirm the existence of errors to the source of data, which may then retransmit the data if required.
Additionally, such a technique requires that the data to be transmitted from the slave to the master be immediately available responsive to SCLK of the master. In an embodiment in which the slave exhibits a plurality of addressable locations, such as addressable registers, in accordance with the prior art a particular slave is selected via an SS pin and an address of the addressable register to be read, denoted the target addressable register, is output by the master. After receipt of the address by the slave, the contents of the target addressable register is retrieved and preferably loaded via an output buffer to the slave shift register to be read out by the master clock. There often exists a latency in the retrieval of the contents of the target addressable register and in one embodiment a wait state is exhibited by the master, delaying the issuance of SCLK thereby supplying time for the slave to retrieve the data from the addressable register. Unfortunately, in certain applications the wait state is insufficient for reliable data retrieval.
There is thus a long felt need for an improved bus arrangement allowing for multiple slaves to be connected to a master without requiring a slave select for each slave. Additionally, there is a need for a communication protocol for use with an SPI bus providing acknowledgement, and preferably providing error detection and notification. There is also a need for a communication protocol for use with an SPI bus exhibiting a reduced sensitivity to delay.